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Core8051
Interrupt Service Routine Unit
Core8051 provides 13 interrupt sources with four priority
levels. Each source has its own request flag(s) located in a
SFR (tcon, scon). Each interrupt requested by the
Special Function Registers
Table 31 displays the Interrupt Enable 0 register (ie0).
corresponding flag can be individually enabled or
disabled by the enable bits in the ien0 and ien1 registers.
There are two external interrupts accessible through pins
Table 31 ? ien0 Register
MSB
LSB
int0 and int1: edge or level sensitive (falling edge or low
eal
–
–
es0
et1
ex1
et0
ex0
level). There are also internal interrupts associated with
Timer 0 and Timer 1, and an internal interrupt from the
serial port.
Table 32 provides the ien0 bit functions.
Table 32 ? ien0 Bit Functions
External Interrupts
Bit
Symbol Function
The choice between external (int0 and int1) interrupt
level or transition activity is made by setting the IT1 and
IT0 bits in the SFR tcon.
When the interrupt event happens, a corresponding
interrupt control bit is set in the tcon register (IE0 or IE1).
This control bit triggers an interrupt if the appropriate
interrupt bit is enabled.
When the interrupt service routine is vectored, the
corresponding control bit (IE0 or IE1) is cleared provided
the edge triggered mode was selected. If level mode is
active, the external requesting source controls flags IE0
7
6
5
4
3
2
1
0
eal
–
–
es0
et1
ex1
et0
ex0
eal=0 – disable all interrupts
Not used for interrupt control
Not used for interrupt control
es0=0 – disable serial channel 0 interrupt
et1=0 – disable timer 1 overflow interrupt
ex1=0 – disable external interrupt 1
et0=0 – disable timer 0 overflow interrupt
ex0=0 – disable external interrupt 0
or IE1 by the logic level on pins int0 or int1 (logic 0 or
logic 1).
During high to low transitions, recognition of an
Table 33 displays the Interrupt Enable 1 register (ien1).
Table 33 ? ien1 Register
interrupt event is possible if both high and low levels last
at least one machine cycle.
MSB
LSB
ex7
ex6
ex5
ex4
ex3
ex2
ex1
ex0
Timer 0 and Timer 1 Interrupts
Timer 0 and 1 interrupts are generated by the TF0 and
TF1 flags in the tcon register, which are set by the
Table 34 provides the ien1 bit functions.
Table 34 ? ien1 Bit Functions
rollover of Timer 0 and 1, respectively. When an interrupt
Bit
Symbol Function
is generated, the flag that caused this interrupt is cleared
if Core8051 has accessed the corresponding interrupt
service vector. This can be done only if the interrupt is
enabled in the ien0 register.
Serial Port Interrupt
The serial port interrupt is generated by logical OR of the
TI and RI flags in the SFR scon. The TI flag is set after the
data transmission completes. The RI flag is set when the
last bit of the incoming serial data was read. Neither RI
nor TI is cleared by Core8051, so the user’s interrupt
7
6
5
4
3
2
1
0
ex7
ex6
ex5
ex4
ex3
ex2
ex1
ex0
ex7=0 – disable int7
ex6=0 – disable int6
ex5=0 – disable int5
ex4=0 – disable int4
ex3=0 – disable int3
ex2=0 – disable int2
ex1=0 – disable int1a
ex0=0 – disable int0a
service routine must clear these flags.
32
v6.0
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